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Methods and apparatus for performing partial reconfiguration in a pipeline-based network topology

机译:在基于管线的网络拓扑中执行部分重新配置的方法和装置

摘要

A programmable integrated circuit that can support partial reconfiguration is provided. The programmable integrated circuit may include multiple processing nodes that serve as accelerator blocks for an associated host processor that is communicating with the integrated circuit. The processing nodes may be connected in a hybrid shared-pipelined topology. Each pipeline stage in the hybrid architecture may include a bus switch and at least two shared processing nodes connected to the output of the bus switch. The bus switched may be configured to route an incoming packet to a selected one of the two processing nodes in that pipeline stage or may only route the incoming packet to the active node if the other node is undergoing partial reconfiguration. Configured in this way, the hybrid topology supports partial reconfiguration of the processing nodes without disrupting or limiting the operating frequency of the overall network.
机译:提供了一种可以支持部分重新配置的可编程集成电路。可编程集成电路可以包括多个处理节点,该多个处理节点用作与集成电路通信的相关联的主处理器的加速器块。可以以混合共享流水线拓扑连接处理节点。混合架构中的每个流水线级可以包括总线开关和连接到总线开关的输出的至少两个共享处理节点。总线交换器可以被配置为将进入的分组路由到该流水线级中的两个处理节点中的选定节点,或者可以仅在另一节点正在进行部分重新配置的情况下才将进入的分组路由到活动节点。通过这种方式配置,混合拓扑支持处理节点的部分重新配置,而不会破坏或限制整个网络的运行频率。

著录项

  • 公开/公告号US10606779B2

    专利类型

  • 公开/公告日2020-03-31

    原文格式PDF

  • 申请/专利权人 ALTERA CORPORATION;

    申请/专利号US201615268281

  • 发明设计人 EVAN CUSTODIO;

    申请日2016-09-16

  • 分类号G06F13/366;G06F9/4401;G06F13/40;G06F15/78;

  • 国家 US

  • 入库时间 2022-08-21 11:28:09

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