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Phase-locked loop, phase-locking method, and communication unit

机译:锁相环,锁相方法和通信单元

摘要

A phase-locked loop of the disclosure includes a detector, an oscillator, an adjuster, and a controller. The detector detects a transition of an input clock signal. The oscillator generates a clock signal having a frequency corresponding to a first control signal, and changes a phase of the clock signal on a basis of a detection result in the detector. The adjuster adjusts a phase difference between a phase of the input clock signal and the phase of the clock signal depending on a second control signal. The controller compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on a basis of a result of the comparison.
机译:本公开的锁相环包括检测器,振荡器,调节器和控制器。检测器检测输入时钟信号的转变。振荡器产生具有与第一控制信号相对应的频率的时钟信号,并基于检测器中的检测结果来改变时钟信号的相位。调节器根据第二控制信号来调节输入时钟信号的相位与时钟信号的相位之间的相位差。控制器在多个比较定时比较输入时钟信号的相位和时钟信号的相位,并基于比较结果生成第一控制信号和第二控制信号。

著录项

  • 公开/公告号US10483989B2

    专利类型

  • 公开/公告日2019-11-19

    原文格式PDF

  • 申请/专利权人 SONY SEMICONDUCTOR SOLUTIONS CORPORATION;

    申请/专利号US201615751094

  • 发明设计人 TAKASHI MASUDA;

    申请日2016-08-15

  • 分类号H03L7;H03L7/083;H03L7/08;H03L7/081;H03L7/087;H03L7/07;H03L7/099;H03L7/091;

  • 国家 US

  • 入库时间 2022-08-21 11:28:11

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