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Effective chip yield for artificial intelligence integrated circuit with embedded memory
Effective chip yield for artificial intelligence integrated circuit with embedded memory
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机译:具有嵌入式存储器的人工智能集成电路的有效芯片良率
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摘要
This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.
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