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Triple-pass execution using a retire queue having a functional unit to independently execute long latency instructions and dependent instructions
Triple-pass execution using a retire queue having a functional unit to independently execute long latency instructions and dependent instructions
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机译:使用具有功能单元的退休队列进行三遍执行,以独立执行长等待时间指令和从属指令
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摘要
An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (ALU) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. The retire queue further includes the third functional unit (e.g., ALU), a reservation station and a graduate buffer. Data dependencies of dependent instructions in the retire queue is handled independently from the main pipeline.
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