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CONDITIONAL EXECUTION SPECIFICATION OF INSTRUCTIONS USING CONDITIONAL EXTENSION SLOTS IN THE SAME EXECUTE PACKET IN A VLIW PROCESSOR
CONDITIONAL EXECUTION SPECIFICATION OF INSTRUCTIONS USING CONDITIONAL EXTENSION SLOTS IN THE SAME EXECUTE PACKET IN A VLIW PROCESSOR
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机译:在VLIW处理器中使用相同执行包中的条件扩展位进行指令的条件执行规范
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摘要
In one embodiment, a system includes a memory and a processor core. The processor core includes functional units and an instruction decode unit configured to determine whether an execute packet of instructions received by the processing core includes a first instruction that is designated for execution by a first functional unit of the functional units and a second instruction that is a condition code extension instruction that includes a plurality of sets of condition code bits, wherein each set of condition code bits corresponds to a different one of the functional units, and wherein the sets of condition code bits include a first set of condition code bits that corresponds to the first functional unit. When the execute packet includes the first and second instructions, the first functional unit is configured to execute the first instruction conditionally based upon the first set of condition code bits in the second instruction.
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