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PHASE LOCKED LOOP CIRCUITS, CLOCK SIGNAL GENERATORS COMPRISING DIGITAL-TO-TIME CONVERT CIRCUITS, OPERATING METHODS THEREOF AND WIRELESS COMMUNICATION DEVICES
PHASE LOCKED LOOP CIRCUITS, CLOCK SIGNAL GENERATORS COMPRISING DIGITAL-TO-TIME CONVERT CIRCUITS, OPERATING METHODS THEREOF AND WIRELESS COMMUNICATION DEVICES
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机译:锁相环电路,包括数字-时间转换电路的时钟信号发生器,其工作方法和无线通信设备
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摘要
Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.
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