DYNAMIC UPDATE OF MACRO TIMING MODELS DURING HIGHER-LEVEL TIMING ANALYSIS

摘要

A system and method involves partitioning a design of an integrated circuit into two or more hierarchical levels. A lowest level includes macros and a higher level includes some or all of the macros. Each of the macros includes two or more components. A macro timing model corresponding with each of the macros indicates a delay through the macro. The macro timing model corresponding with ones of the macros that are part of the higher level are loaded to perform higher-level timing analysis, which indicates a delay through the ones of the macros that are part of the higher level. Modified macro timing models corresponding with one or more of the macros are generated, and only the modified macro timing models associated with the macros that are part of the higher level modify corresponding loaded macro timing models to continue the higher-level timing analysis.