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FAULT DETECTABLE AND TOLERANT NEURAL NETWORK

机译:故障可检测且可容忍的神经网络

摘要

A hardware neural network engine which uses checksums of the matrices used to perform the neural network computations. For fault correction, expected checksums are compared with checksums computed from the matrix developed from the matrix operation. The expected checksums are developed from the prior stage of the matrix operations or from the prior stage of the matrix operations combined with the input matrices to a matrix operation. This use of checksums allows reading of the matrices from memory, the dot product of the matrices and the accumulation of the matrices to be fault corrected without triplication of the matrix operation hardware and extensive use of error correcting codes. The nonlinear stage of the neural network computation is done using triplicated nonlinear computational logic. Fault detection is done in a similar manner, with fewer checksums needed and correction logic removed as compared to the fault correction operation.
机译:硬件神经网络引擎,使用用于执行神经网络计算的矩阵校验和。为了进行故障校正,将期望的校验和与从矩阵运算得出的矩阵计算出的校验和进行比较。预期校验和是从矩阵运算的前一级或从矩阵运算的前级与输入矩阵组合而形成的。校验和的这种使用允许从存储器中读取矩阵,矩阵的点积以及要进行故障校正的矩阵的累积,而无需矩阵运算硬件的三倍重复和纠错码的广泛使用。神经网络计算的非线性阶段是使用三重非线性计算逻辑完成的。与故障校正操作相比,以相似的方式进行故障检测,所需的校验和更少,并且删除了校正逻辑。

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