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LAYOUTS FOR FAULT-TOLERANT QUANTUM COMPUTERS
LAYOUTS FOR FAULT-TOLERANT QUANTUM COMPUTERS
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机译:容错量子计算机的布局
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摘要
Disclosed herein are example layouts and layout generation techniques for fault-tolerant quantum computers. Example embodiments comprise methods for performing a layout reduction technique for fault-tolerant quantum computing. In certain embodiments, a layout of an arbitrary quantum circuit is reduced to a layout of exponents of a multiple qubit Pauli matrix and measurements of a multiple qubit Pauli matrix. In certain embodiments, qubits are marked as one of a data, interface, or ancilla qubit for a 2D nearest neighbor graph of qubit connectivity, and an ancilla-path is provided from a respective data qubit to a respective interface qubit.
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