DECISION FEEDBACK EQUALIZATION WITH INDEPENDENT DATA AND EDGE FEEDBACK LOOPS

摘要

A receiver module (110) includes a clock recovery circuit (116) and a decision feedback equalizer (DFE) circuit (112). The DFE circuit (112) includes a data feedback loop (130) configured to sample an input data stream combined with equalization values based on a first clock signal (CLK1). The DFE circuit (112) also includes an edge feedback loop (140) configured to sample the input data stream combined with equalization values based on a second clock signal (CLK2). The clock recovery circuit (116) is configured to determine a phase error between a receiver clock signal and a target clock signal based on output samples from the data feedback loop (130) and the edge feedback loop (140).