CLOCK CYCLE-BASED PULSE WIDTH MODULATION SIGNAL DUTY CYCLE MULTIPLICATION CIRCUIT

摘要

A clock cycle-based pulse width modulation signal duty cycle multiplication circuit, comprising: a duty cycle multiplication enabling pulse generating circuit (101), an input end thereof inputting a clock signal (CLK) and an original pulse width modulation signal (PWM1), the duration of a high level and low level of the original pulse width modulation signal (PWM1) being the sum of an integer number of clock cycles of the clock signal (CLK), while an output end outputs a PWM multiplication start enabling pulse signal (Pulse1) and a PWM multiplication end enabling pulse signal (Pulse2); and a duty cycle multiplication circuit (102), an input end thereof inputting the PWM multiplication start enabling pulse signal (Pulse1) and the PWM multiplication end enabling pulse signal (Pulse2), and an output end outputting a PWM multiplication pulse width modulation signal (PWM2); the pulse width of the pulse width modulation signal after duty cycle multiplication (PWM2) is adapted to the PWM multiplication start enabling pulse signal (Pulse1) and the PWM multiplication end enabling pulse signal (Pulse2), and the pulse width modulation signal after duty cycle multiplication (PWM2) performs signal synchronization by means of the clock signal (CLK) to ensure that the duration of both a high level and low level of the pulse width modulation signal after duty cycle multiplication (PWM2) is the sum of an integer number of clock cycles of the clock signal (CLK). By means of synchronizing the original pulse width modulation signal (PWM1) and on the basis of a clock cycle, by cooperating with a corresponding control circuit, it is very convenient to achieve a duty cycle multiplication function for PWM signals.