DELAY TIME DETECTION CIRCUIT, TIMESTAMP INFORMATION GENERATION DEVICE, AND DELAY TIME DETECTION METHOD

摘要

This delay time detection circuit comprises a clock generation unit (11), counting unit (12), subscale signal generation unit (13), and delay time calculation unit (14). The clock generation unit (11) generates a subscale clock signal on the basis of a system clock signal. The counting unit (12) generates a count signal while sequentially and repeatedly incrementing by a preset counting number on the basis of the subscale clock signal. The subscale signal generation unit (13) receives the count signal and generates a number of subscale signals equal to the counting number that have, in a one-to-one ratio with the counting number, square waves of a duration corresponding to a second period and timings that are shifted according to the second period. The delay time calculation unit (14) receives an input clock signal and calculates the delay time, within a first period, of the input clock signal in relation to the system clock signal on the basis of one subscale signal having a timing matching that of the input clock signal.