PERFORMANCE MODELING AND ANALYSIS OF MICROPROCESSORS USING DEPENDENCY GRAPHS

摘要

Embodiments described herein are directed to a microarchitecture modeling tool configured to model and analyze a microarchitecture using a dependency graph. The dependency graph may be generated based on an execution trace of a program and a microarchitecture definition that specifies various features and/or characteristics of the microarchitecture on which the execution trace is based. The dependency graph includes vertices representing different microarchitectural events. The vertices are coupled via edges representing a particular dependency therebetween. The edges are associated with a cost for performing microarchitectural event(s) corresponding to the vertices coupled thereto. The dependency graph also takes into account various policies for structural hazards of the microarchitecture. The microarchitecture modeling tool analyzes the costs associated with each of the edges to determine a design metric of the microarchitecture. A user is enabled to modify various features of the dependency graph to analyze different design choices and/or optimizations to the microarchitecture.