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NOVEL METHOD TO COMPUTE TIMING YIELD AND YIELD BOTTLENECK USING CORRELATED SAMPLE GENERATION AND EFFICIENT STATISTICAL SIMULATION
NOVEL METHOD TO COMPUTE TIMING YIELD AND YIELD BOTTLENECK USING CORRELATED SAMPLE GENERATION AND EFFICIENT STATISTICAL SIMULATION
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机译:相关样本生成和有效统计模拟的产量和产量瓶颈时序计算新方法
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摘要
Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.
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