Method and apparatus for reducing the effects of transistor random mismatch in a circuit

摘要

An analog circuit comprising a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit comprising an input node, an output node, a phase controller for timing even and odd phases, an input switch and an output switch. The input switch electrically connects the mismatch reducing circuit input node to the first node of the analog circuit input node pair during each even phase and electrically connects the mismatch reducing circuit input node to the second node of the analog circuit input node pair during each odd phase. do. The output switch electrically connects the first node of the analog circuit output node pair to the mismatch reduction circuit output node during each even phase and the second node of the analog circuit output node pair to the mismatch reduction circuit output node during each odd phase. do.