RQL majority gates, AND gates, and OR gates

摘要

The mutual quantum logic (RQL) gate circuit has an input stage with logic inputs asserted based on receiving positive single flux quantum (SFQ) pulses, and an amplified output stage comprising a JTL for conveying an output signal. . The input stage includes two or more storage loops, at least two of which are each associated with a logic input, each of which includes an input Josephson junction (JJ), a storage inductor, and a logic decision JJ, and the logic decision JJ is , The logic inputs and associated storage loops are configured to be triggered based on a biasing signal provided to the circuit and a biasing provided by one or more currents stored in the storage loops. The output stage asserts the output based on the triggering of the logic decision JJ.