Off-chip distributed drain biasing of high power distributed amplifier single high frequency integrated circuit chips

摘要

Off-chip distributed drain biasing increases output power and efficiency for high power dispersion amplifier MMICs. The off-chip bias circuit has a common input for receiving a DC bias current and a plurality of parallel connected bias chokes to which the DC bias current is divided. The chokes connect a plurality of drain terminals in different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier, and the load impedance identified at the drain terminal to improve power and efficiency is better for the amplifier stages. The inductances are added to the FET amplifier stages selected to change to match, typically early stages.