SAR A SAR ANALOG DIGITAL CONVERTOR WITH LOW POWER AND HIGH PERFORMANCE CHARGE REDISTRIBUTION

摘要

The present invention relates to a successive approximation register (SAR) analog to digital converter (ADC) having a low-power and high-performance charge redistribution function. More particularly, the present invention relates to an SAR ADC capable of realizing low-power and high-performance charge redistribution by using a sample and hold circuit built in a digital analog converter (DAC) without using a separate sample and hold circuit to minimize the power consumption of the SAR ADC used in living implant devices or the like, and also by using a two-stage binary weighted capacitor array.