Design of low power high speed SAR based 16-bit analog to digital converter: Charge sharing approach

摘要

This paper presents a high speed low power successive approximation register (SAR) based analog-to-digital converter (ADC) using Charge-Sharing (CS) principle. SARs critical path plays a vital role in high speed application of ADCs. A 16-bit SAR array with reduced critical path delay is proposed to obtain delay of 60ps, along with charge-sharing ADC incorporated with low-voltage low-power double-tail comparator (LV-LPDTC), is proposed in 45nm CMOS to convert 10 MSps at 600 mV supply voltage and 40MSps when supply voltage raised by 66.67%. The SAR controller array consumed 16.47 μW, which leads to a overall power consumption of 149.1 μW. The measured effective-number-of-bits is 15.1, confined to a FoM of 70.76 fJ/conversion-step.