STT-MRAM APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE

摘要

An apparatus is described, which comprises: a first select-line; A second select-line; Bit-line; A first bit-cell comprising a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; A buffer having an input coupled to the first select-line and an output coupled to the second select-line; And a second bit-cell comprising a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. A magnetic random access memory (MRAM) comprising a plurality of rows is described, each row comprising: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; And a plurality of buffers, each buffering a select-line signal for a group of bit-cells among the plurality of bit-cells; And a plurality of bit-lines, each row sharing a single bit-line between the plurality of bit-cells in the row.