DRAM controller having bad pages management function and therefore bad pages management method

摘要

An improved bad page management technique is disclosed to guarantee the yield of a volatile semiconductor memory device such as DRAM. Inside the DRAM, only the bad page list exists. In the memory controller, the page remapper performs a page remapping operation in parallel with the normal operation of the scheduling unit for a latency overhead hidden function. The chip size overhead of the DRAM is reduced or minimized, and the DRAM controller has a latency overhead hidden function to control the DRAM.