SHARING VIRTUAL AND REAL TRANSLATIONS IN A VIRTUAL CACHE

摘要

Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory contains a plurality of directory entries, each entry is assigned to a cache line. Each cache line has a tag. The tag contains a logical address, an address space identifier, a bit indicator of a real address and an indicator from virtual address to real address. This virtual address to real address indicator indicates whether the logical address and the real address are the same. When activated, no address translation is carried out.