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SYSTEMS AND METHODS FOR TRAINING A THIN FILM RESISTOR INTEGRATED IN AN INTEGRATED CIRCUIT ARRANGEMENT

机译:培训集成在集成电路布置中的薄膜电阻的系统和方法

摘要

A method of forming a thin film integrated resistor (TFR) in a semiconductor integrated circuit device is provided. A first dielectric layer is deposited on an integrated circuit structure (IC structure) with conductive contacts, a resistance film (e.g. made of SiCCr, SiCr, CrSiN, TaN, TaSi or TiN) is deposited over the first dielectric layer, the resistance film etched to define the dimensions of the resistive film, and a second dielectric layer is deposited over the resistive film so that the resistive film is between the first and second dielectric layers. A connection trench layer may be deposited over the second dielectric layer and etched, for example, using a single mask to define openings that expose surfaces of the IC pattern contacts and the resistance film. The openings can be covered with a conductive connecting material, e.g. As copper, are filled to contact the exposed surfaces of the conductive contacts and the resistance film.
机译:提供了一种在半导体集成电路器件中形成薄膜集成电阻器(TFR)的方法。将第一介电层沉积在具有导电触点的集成电路结构(IC结构)上,将电阻膜(例如,由SiCCr,SiCr,CrSiN,TaN,TaSi或TiN制成)沉积在第一介电层上,蚀刻电阻膜为了限定电阻膜的尺寸,在电阻膜上沉积第二介电层,使得电阻膜在第一和第二介电层之间。连接沟槽层可以沉积在第二介电层上并且例如使用单个掩模来蚀刻以限定暴露IC图案触点和电阻膜的表面的开口。开口可以覆盖有导电连接材料,例如绝缘材料。作为铜,被填充以接触导电触点和电阻膜的暴露表面。

著录项

  • 公开/公告号DE112018003821T5

    专利类型

  • 公开/公告日2020-04-09

    原文格式PDF

  • 申请/专利权人 MICROCHIP TECHNOLOGY INCORPORATED;

    申请/专利号DE20181103821T

  • 发明设计人 PAUL FEST;

    申请日2018-07-24

  • 分类号H01L49/02;H01L23/522;H01L27/06;

  • 国家 DE

  • 入库时间 2022-08-21 11:01:32

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