The use of a non-volatile memory array architecture to implement a binary neural network (BNN) enables matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as memory cells with a programmable resistor, which are each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values to word line pairs connected to the unit synapses to multiply the input by weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, the results being accumulated by a summation circuit. The approach can be expanded from binary weights to multi-bit weight values by using multiple differential memory cells for one weight.
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