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NEURONAL CIRCUIT CAPABLE OF IMPLEMENTING SYNAPTIC LEARNING

机译:实施突触学习的神经回路能力

摘要

A synaptic integration circuit (30) for a neuromorphic chip includes a resistive memory synapse (S1-S3) which has an activation terminal (BA) for receiving a presynaptic action signal (Sa3 ) and a propagation terminal (BP) intended to be connected to said circuit to transmit a synaptic output signal which depends on the resistance of said memory. The circuit includes an accumulator (Cm) of the synaptic output signal, a comparator (Comp) configured to emit a postsynaptic pulse (So) if a threshold (Vm) is crossed by the accumulated output signal. It is also configured, when a presynaptic action signal is applied to the activation terminal, to impose a conductance modification voltage on the synapse by applying a postsynaptic action signal to the propagation terminal. Figure for the abstract: Figure 7
机译:用于神经形态芯片的突触集成电路(30)包括电阻性记忆突触(S1-S3),其具有用于接收突触前动作信号(Sa3)的激活端子(BA)和打算与之连接的传播端子(BP)所述电路传输取决于所述存储器的电阻的突触输出信号。该电路包括突触输出信号的累加器(Cm),比较器(Comp),比较器(Comp)配置为如果阈值(Vm)被累加的输出信号越过,则发出突触后脉冲(So)。还配置为,当将突触前动作信号施加到激活端子时,通过将突触后动作信号施加到传播端子,在突触上施加电导改变电压。图为摘要:图7

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