A system for firmware protection and validation includes: a memory device, including firmware; a chipset, a microprocessor; a secure logic device in electrical communication with the chipset and the memory device; and a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset, when the hold signal is applied to the chipset, the power on reset circuit de-asserts the reset signal, when the reset signal is de-asserted, the secure logic device validates the content of the firmware in the memory device, and further wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the hold signal applied to the chipset.
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