首页> 外国专利> Memory sharing for buffered macro-pipelined data plane processing in multicore embedded systems

Memory sharing for buffered macro-pipelined data plane processing in multicore embedded systems

摘要

Disclosed are an apparatus and method of operating and allocating a shared memory between various applications operating via a processing computing platform. One example may include receiving a first buffer context switch request message from a first application operating via a processor, transmitting a first buffer context switch flag to the processor operating the application confirming the first buffer context switch request was received, receiving a second buffer context switch request from a second application with a different processing cycle operating via the processor and transmitting a second buffer context switch flag to the processor operating the second application confirming the second buffer context switch request was received. Once the applications have been identified and confirmed, a synchronization operation may be performed to create a shared number of memory units between at least two different buffers and provide the shared memory units to the first application and the second application.

著录项

  • 公开/公告号US10659534B1

    专利类型

  • 公开/公告日2020.05.19

    原文格式PDF

  • 申请/专利权人

    申请/专利号US15949426

  • 发明设计人 Russell C. McKown;

    申请日2018.04.10

  • 分类号

  • 国家 US

  • 入库时间 2022-08-21 10:59:09

相似文献

  • 专利
  • 外文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号