Latch circuit and flip-flop circuit with single event upset resistance

摘要

Provide a latch circuit and a flip-flop circuit with superior single event upset (SEU) resistance.A latch circuit having a single event upset (SEU) resistance of the present inventionFor eight transistors composing a conventional dice latch circuitRespectivelyTo double the serialized Series in parallelSeriesParallelBy adding transistors that are redundant to three locations in series and series parallelEach transistor is replaced with four transistors.The first data input portion and the second data input portion are also double redundant.