System and method for retaining DRAM data when reprogramming a reconfigurable device with a DRAM memory controller incorporating a data maintenance block co-located with a memory module or subsystem

摘要

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming a reconfigurable device using a DRAM memory controller, such as a field programmable gate array (FPGA). The DRAM memory controller is used in conjunction with a data maintenance block that is co-located with the DRAM memory and coupled to the I2C interface of the reconfigurable device, and the FPGA drives most DRAM input / output (I / O) The data maintenance block then drives the self-refresh command input. Even if the FPGA reconfigures and most DRAM inputs are tri-stated, the data maintenance block provides a stable input level for self-refresh command input.