METHOD FOR INTEGRATING PARALLELABLE POWER CHIPS AND ELECTRONIC POWER MODULES

摘要

The method comprises 1) an embodiment of first and second blanks (EB1) including a use of space reservation means (HM1, HM2), by lamination of insulating and conductive inner layers (PP, CP) on copper plates forming base (MB1), at least one electronic chip being implanted sandwiched between the blanks which are made with complementary profiles of their high lamination surfaces, 2) a stack and interlocking of the blanks by their complementary profiles, and 3) an assembly with the press blanks to achieve a laminated subassembly for an integrated electronic power device. The method uses the use of so-called IMS techniques.