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ARCHITECTURE DE RÉCEPTEURS POUR LECTURES EN MÉMOIRE
ARCHITECTURE DE RÉCEPTEURS POUR LECTURES EN MÉMOIRE
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摘要
A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.
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