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Execution model and optimizing compilation for execution migration

机译:执行模型和优化编译以执行迁移

摘要

Although systems with hardware support for fine-grained execution migration are becoming a reality, no concrete execution model or compiler exist for these machines. This limits the complexity of software that can be written for these machines, and therefore also the scope of studies for which these machines can be used. In this thesis, we define a productive programming model for an execution migration platform by exposing migration as a set of interfaces usable with the C programming language via a custom optimizing compiler. We employ hardware-software co-design to describe a stack core architecture with support for partial context migration in order to simplify the compiler problem and improve compiler efficiency. We also consider instruction encoding in abstract terms to establish a baseline comparison of encoded instruction density to an ideal upper bound. The stack-based execution migration platform offers a new and unexplored cost model, which leads us to reevaluate the trade-offs associated with compilation for these architectures, and to explore novel algorithms, or novel applications of existing optimizations. Throughout this work, we attempt to gain a deep understanding of the costs and benefits of execution migration by aggressive design space exploration. We use the insight gained to better inform the the problem of compiling to this unorthodox architecture, and design the compiler, a library of optimized parallel primitives, and a set of compiler optimization passes to best reflect and utilize the underlying hardware.
机译:尽管具有支持细粒度执行迁移的硬件的系统已成为现实,但这些机器尚不存在具体的执行模型或编译器。这限制了可以为这些机器编写的软件的复杂性,因此也限制了可以使用这些机器的研究范围。在本文中,我们通过定制优化编译器将迁移公开为可与C编程语言一起使用的一组接口,从而为执行迁移平台定义了高效的编程模型。我们采用软硬件协同设计来描述支持部分上下文迁移的堆栈核心体系结构,以简化编译器问题并提高编译器效率。我们还以抽象的方式考虑指令编码,以建立编码指令密度与理想上限的基线比较。基于堆栈的执行迁移平台提供了一个新的且尚未开发的成本模型,这使我们重新评估了与这些体系结构的编译相关的权衡,并探索了新颖的算法或现有优化的新颖应用。在整个工作中,我们试图通过积极的设计空间探索来深入了解执行迁移的成本和收益。我们使用获得的见解更好地告知针对这种非传统体系结构的编译问题,并设计编译器,优化的并行原语库以及一组编译器优化通道,以最好地反映和利用底层硬件。

著录项

  • 作者

    Lebedev Ilia Andreevich;

  • 作者单位
  • 年度 2013
  • 总页数
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类

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