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Design of the Trap Filter for the High Power Converters with Parallel Interleaved VSCs

机译:并联交错型VsC大功率变换器陷阱滤波器的设计

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摘要

The power handling capability of the state-of-the-art semiconductor devices is limited. Therefore, the Voltage Source Converters (VSCs) are often connected in parallel to realize high power converter. The switching frequency semiconductor devices, used in the high power VSCs, is also limited. Therefore, large filter components are often required in order to meet the stringent grid code requirements imposed by the utility. As a result, the size, weight and cost of the overall system increase. The use of interleaved carriers of the parallel connected VSCs, along with the high order line filter, is proposed to reduce the value of the filter components. The theoretical harmonic spectrum of the average pole voltage of two interleaved VSCs is derived and the reduction in the magnitude of some of the harmonic components due to the carrier interleaving is demonstrated. A shunt LC trap branch is used to sink the dominant harmonic frequency components. The design procedure of the line filter is illustrated and the filter performance is also verified by performing the simulation and the experimental study.
机译:现有技术的半导体器件的功率处理能力受到限制。因此,电压源转换器(VSC)通常并联连接以实现高功率转换器。在高功率VSC中使用的开关频率半导体器件也受到限制。因此,通常需要大的过滤器组件才能满足公用事业公司提出的严格的网格代码要求。结果,整个系统的尺寸,重量和成本增加。提出了使用并联连接的VSC的交错载波以及高阶线路滤波器,以减小滤波器组件的值。推导了两个交错VSC的平均极点电压的理论谐波频谱,并证明了由于载波交错而导致的某些谐波分量的幅度减小。并联LC陷波分支用于吸收主谐波频率分量。通过进行仿真和实验研究,说​​明了线路滤波器的设计过程,并验证了滤波器的性能。

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