High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis

摘要

Despite significant performance and power advantagescompared to microprocessors, widespread usage of FPGAshas been limited by increased design complexity. High-levelsynthesis (HLS) tools have reduced design complexity but providelimited support for verification, debugging, and timing analysis.Such tools generally rely on inaccurate software simulation orlengthy register-transfer-level simulations, which are unattractiveto software developers. In this paper, we introduce HLS techniquesthat allow application designers to efficiently synthesizecommonly used ANSI-C assertions into FPGA circuits, enablingverification and debugging of circuits generated from HLS tools,while executing in the actual FPGA environment. To verify thatHLS-generated circuits meet execution timing constraints, weextend the in-circuit assertion support for testing of elapsedtime for arbitrary regions of code. Furthermore, we generalizetiming assertions to transparently provide hang detection thatback annotates hang occurrences to source code. The presentedtechniques enable software developers to rapidly verify, debug,and analyze timing for FPGA applications, while reducing frequencyby less than 3% and increasing FPGA resource utilizationby 0.7% or less for several application case studies on the AlteraStratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C.The presented techniques reduced area overhead by as much as3x and improved assertion performance by as much as 100%compared to unoptimized in-circuit assertions.