The Architecture of a Large Distributed Logic Associative Memory.

摘要

The design of a processor for information storage and retrieval is considered. At the same time, the properties of a distributed logic stored program iterative associated processor are investigated. The capability to segment such a processor into independently acting units is clearly desirable. Two techniques for segmenting such a processor with a tree structure are presented here and are shown to make it economically promising for information retrieval. The tree structure is found to have short propagation delays so that a large processor might be feasible. The use of pushdown stacks in generating instructions in this processor is explored. The instruction set is improved somewhat over that of previous associative processors for more efficient retrieval. Considerable attention is given to representation structures which are particularly suited for describing complex data base. (Author)