Enabling CTS (Clear-to-Send) Handshaking on the Intel 8251A USART in Asychronous Polled Mode

摘要

The Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides microprocessors with a programmable communications interface to serial lines. When used with external devices which can accept data at all times at the selected baud rate, the 8251A can fully utilize the available bandwidth by internal double-buffering of the transmitted data. When used with devices such as fast serial printers, which require a ready-resume handshake via a Clear-To-Send (CTS) lead, this double buffering can cause loss of characters. In many, if not most, systems a software solution is available. The 8251A brings the Data-Set-Ready (DSR) lead into its status word, as bit 7, and provides a Transmit-Buffer-Empty (TxEmpty) status bit, bit 3. If CTS is bridged to DSR and no transmission is done until DSR, TxEmpty, and Transmit Ready (TxRDY) are all set to one, then the remote handshake will be honored. In some systems, however, the software is not available for alteration, and a hardware solution is desirable. This note shows how to modify the 8251A support circuitry, so that the TxRDY bit reported to the CPU carries all the necessary information for a CTS handshake. (ERA citation 08:056795)