Design of High Performance Digital Arithmetic Units

摘要

The author has designed the arithmetic hardware of the S-1 Mark IIA uniprocessor system. The Mark IIA average throughput approaches that of a Cray-1 when doing floating-point-intensive computations, but also computes at very high performance levels when doing most other types of modern digital data processing. The goal of the Mark IIA design effort has been to realize a computing system with its capabilities distributed in a balanced fashion throughout the spectrum of modern digital computing interests. Several of the techniques used in this effort at balanced high-performance processor design are original and are described herein. In addition, an attempt has been made to describe why these techniques are useful and, since their relative values often depend upon choices that were made during the definition of the architecture to be implemented and of its high-level design, the rationale underlying these decisions is also sketched. 37 refs., 39 figs.