Design of Low-Power, High-Resolution, Analog-to-Digital Conversion Systems with Sampling Rates Less Than 1 KHz

摘要

In recent years, there has been increased usage of microprocessor-based, real-time, signal processing systems in field applications. In such systems, which operate off limited power sources, the high power consumption of the analog-to-digital converter and the associated sample-and-hold amplifier has severely restricted the operating period due to short battery lifetimes. The need for a high resolution analog-to-digital conversion system which could operate at moderate speeds with low power consumption is apparent. This paper discusses the design and evaluation of two systems incorporating techniques which partly solve this problem. The techniques are low duty-cycle power switching to reduce power consumption, and performing iterative conversions to obtain increased resolution. (ERA citation 11:006761)