FASTBUS Flash ADC System for the Mark II Vertex Chamber.

摘要

This is a description of a flash ADC system built for the Mark II experiment at the Stanford Linear Accelerator Center (SLAC). This system was designed for use in the experiment's vertex chamber where signals could occur over a relatively long time, approximately 10 microseconds. This long time, coupled with fast cable amplifiers, necessitated an alternate design approach than was used with a dE/dX FASTBUS flash ADC design. 1 ref., 6 figs. (ERA citation 14:005034)