Electrochemical planarization for microelectronic circuits.

摘要

The need for flatter and smoother surfaces (planarization) in microelectronic circuits increases as the number of metal levels in ultra large scale integrated (ULSI) circuits increases. At Lawrence Livermore National Laboratory, the authors have developed an electrochemical planarization process that fills vias and trenches with metal (without voids) and subsequently planarizes the surface. Use is made of plasma-enhanced chemical vapor deposition (PECVD) of SiO(sub 2) for the dielectric layers and electroplated copper for the metalization. This report describes the advantages of this process over existing techniques, possibilities for collaboration, and previous technology transfer.