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High Speed Electronic Bit Synchronizer.

机译:高速电子位同步器。

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Communications by means of mode-locked lasers requires a bit synchronizer at the receiver capable of detecting an RZ pulse stream at a data rate of 1.0 gigabit/second. A synchronizer meeting these requirements was designed,constructed,and tested under contract to the Air Force Avionics Laboratory,Wright Field,Ohio. The report presents a description of the synchronizer and highlights significant advances in circuit technology that were developed. Of particular note is the discussion of the theory and design of a passive microstrip filter that performs a continuous integrate and dump operation with an RZ signal. Other circuit developments of significance include a hybrid sample-and-hold device having an aperture time less than 40 picoseconds and an automatic threshold circuit that continuously adjusts the decision level in an optimum fashion. The testing and evaluation of high speed bit synchronizers is given strong emphasis in this report. A laser link simulator was designed and constructed,and a description of it is presented. Models of mode-locked laser links are explored,and the techniques for simulating Poisson background noise,extinction ratio,and other link parameters are described. The setting up of any given set of test conditions in the laboratory is necessarily a complex operation,and all steps of such a procedure are carefully outlined. This is followed by the presentation of test data in the form of bit error rate graphs and the various error sources are analyzed and explained. It is concluded that performance degradation of 3to 6db from theoretically optimum detection can occur because of imperfections in the link simulation and loss of energy due to circuit bandwidth limitations.

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