Controlled Inversion Devices.

摘要

Application and theory of Inversion Controlled Switch (ICS) devices (which we previously called 'Controled Inversion Devices') were investigated. Random access memory arrays of discrete devices were constructed in order to test memory array design. Each memory cell had only a single active device. Examination of the current voltage characteristics of the ICS memory cell and experiments on 3 x 3, 1 x 5 and 5 x 1 arrays lead to several refinements of cell design, the most important one being the use of diode isolation of device bases. This final circuit design effectively prevented all unwanted interactions between different memory cells. Using the circuit design, a simple 2 x 2 integrated array was designed. The integrated circuit made use of buried layer emitter, junction isolation and amorphous germanium load resistors which were deposited directly on top of device collector contacts. The basic ICS structure chosen for this circuit were molybdenum-SiO2-n-p(+) devices. The circuit fabrication required seven masking steps including the one required to define the buried emitters. Fabrication studies revealed that most difficulties encountered were due to steps which were not connected with the active ICS device itself. Six wafers were processed. The final wafer had 100% yield except for damages incurred in probing. The array worked as expected as a static memory with non-destructive read out. Read, write and erase functions could be accomplished with only small incremental power requiements above that needed for holding information.