Alpha Structure Based B-HIVE Multicomputer

摘要

This paper describes the design and implementation of the B-HIVE multicomputer, a 24-node generalized hypercube being constructed at North Carolina State University. Each node in B-HIVE consists of a pair of tightly coupled micro computers: a National Semiconductor DB32016 processor with MMU and FPU to serve as the application processor, and an Intel 80186 processor to handle intra-nodal communications. Intra-nodal communications is via dual ported RAM. The hardware is designed to primarily support packet switched communications between nodes, but also have the capability to support a limited number of dynamically configurable circuit switched channels, as well, A demand driven virtual paging mechanism has been incorporated into the design to provide inter-nodal communications which is transparent to the application software. More direct message passing via system call is supported as well.