Design and Performance of the Rollback Chip: Hardware Support for Time Warp

摘要

The Time Warp mechanism offers an elegant approach to attacking difficult clock synchronization problems that arise in applications such as parallel discrete event simulation. However, because Time Warp relies on a lookahead and rollback mechanism to achieve widespread exploitation of parallelism, the state of each process must periodically be saved. Existing approaches to implementing state saving and rollback are not appropriate for large Time Warp programs. A component called the Rollback Chip (RBC) is proposed in this thesis to efficiently implement these functions. Such a component could be used in a programmable, special purpose parallel discrete event simulation engine based on Time Warp. The algorithms implemented by the rollback chip are described, as well as mechanisms that allow efficient implementation. Results of simulation studies are presented. These results show that the rollback can virtually eliminate the state saving and rollback overheads that plague current software implementations of Time Warp. Theses. (RH)