Design of a Hardware Discrete Event Simulation Coprocessor

摘要

A hardware discrete event simulation (DES) coprocessor was designed to eliminatesynchronization overhead as a possible bottleneck. The target architecture is an eight node Intel iPSC/2 Hypercube, but this design has application to future CPU designs that wish to incorporate on-chip architectural features to better support parallel processor synchronization. A structural description of a general-purpose DES hardware coprocessor is given with approximately 90 percent of the components written at the gate level. The remaining components use low-level behavioral descriptions. While the DES coprocessor microcode implements the Chandy-Misra protocol, general-purpose support for a wide-range of protocols was a primary hardware design objective.... Simulation, Parallel processing, Discrete event simulation, VHDL, Coprocessor, Simulation accelerator.