A new architecture to improve the SNR of the readout circuit for capacitive TSPs is introduced. The architecture shows better performance in spite of requiring less power consumption and using an integration capacitor that is roughly half in size compared with a previous work. It averages noises by repeated integration and substantially mitigates the effect of display noise through a differential sensing technique. Furthermore, it does not require additional calibration circuitry to correct the settling error by different delay paths because two adjacent lines in differential sensing have almost the same R-C time constant. The circuit is designed in a 0.35μm CMOS technology.
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