3D processing on 6 in. high resistive SOI wafers: Fabrication of edgeless stripand pixel detectors

摘要

An insight is given into the state-of-the-art 3D processing on 6 in. (150 mm) high resistivity silicon-on-insulator (S01) wafers. The edgeless detector design offers some attractive properties for high-energyphysics experiments and medical imaging studies, such as seamless tileability of the detectors with aninactive region width of about 10μm. These detectors can be made very thin and the active edge avoidsinhomogeneous electric fields and surface leakage currents.The paper summarizes the fabrication of edgeless detectors and the issues faced in the 3Dprocessing on 6 in. SOI wafers. The fabrication process employed highly doped polysilicon filling in orderto implement the active edges of the detector. Several planarization and ICP-etching steps wererequired. The layout had microstrip detectors with a pitch of 50μm and sizes of 5 x 5 cm~2and 1 x cm~2,and Medipix2 compatible 1.4 x 1.4 cm~2pixel detectors. Also several test structures were fabricated.Electrical characterization of a 150-μm-thick edgeless diode showed low leakage currents, below1 nA/cm~2at full depletion. The single-strip measurements showed leakage currents of about 10 pA/cm,regardless of the detector size. Low breakdown voltage of about 20 V was observed for several detectors.This might be caused by cracking of the detector edges following self-dicing. A simplified process flowfor the fabrication of edgeless detectors is presented. The process is straightforward and fast because itexcludes multiple ion coupled plasma (ICP)-etching steps, slow and wafer-damaging polysilicon fillingand planarization steps. First images of the prototype are presented.