Algorithms and hardware description languages in railway interlocking logic design

摘要

Despite years of railway control and signalling development, modern formal description methods are still not widely used. Lack of standards in the interlocking logic construction method causes the development of the railway control systems to be more and more expensive. Moreover, the microprocessor technology used nowadays reaches its limits regarding signal processing time in decentralised systems. This forces the industry to seek for new solutions. This paper presents an algorithmic approach to interlocking logic development, together with a modern implementation methods using hardware description languages and programmable devices.