Resistivity measurements of intentionally and unintentionally template-grown doped silicon nanowire arrays

摘要

High density, intentionally doped silicon nanowire (SiNW) arrays were fabricated within the pores of anodic alumina (AAO) templates via gold-catalysed vapour-liquid-solid (VLS) growth using silane (SiH_4) as the source gas and trimethylboron ((CH_3)_3B, TMB) and phosphine (PH_3) as p-type and n-type dopant sources, respectively. The AAO template serves as a support structure for nanowire growth and fabrication of electrical contacts to the nanowire arrays. Nanowire array resistance was measured as a function of SiNW length for a series of samples prepared with different dopant/SiH_4 inlet gas ratios. A method was developed to extract the SiNW resistivity from the measurements of array resistance versus nanowire length. The nanowire resistivity measured from the arrays decreased with increasing dopant/SiH_4 ratio and compared favourably with resistivity data obtained from four-point measurements of individual SiNWs grown under identical conditions. Nominally undoped SiNWs grown in the AAO templates were found to be p-type with resistivity in the range of 1-3 OMEGA cm, indicating the presence of unintentional acceptors in the wires. The resistivity of undoped SiNWs grown under identical conditions but on oxidized (100) Si substrates was much higher, of the order of 10~4-10~5 OMEGA cm, suggesting that the AAO templates are the source of the acceptor impurities.