Modelling single-electron-transistor-based readout in the Kane solid-state quantum computer

摘要

The Kane (Kane B E 1998 Nature 393 133) solid-state quantum computer aims to exploit as qubits an array of ~(31)P nuclear spins embedded in a silicon matrix. A proposed scheme for readout of a qubit spin state relies on measurement of the associated spin state of its donor electron, by attempting 80 induce and detect, using a single-electron transistor (SET), spin-polarized motion of the electron to an adjacent donor site. The sensitivity required of a SET for detection of sub-surface electronic charge motion in a MOS architecture is examined by simulation of the capacitive coupling of the buried charge to the SET device. It is shown that the SET can support readout of the qubit electronic charge states within the appropriate electron spin relaxation time. This paper presents a novel application of Technology Computer Aided Design, which presents itself as a valuable tool for the design of nanoscale device architectures employing precision electrometry for readout of quantum logic states.